1. Field of the Invention
This invention relates to semiconductor fabrication process, and more particularly, to a method for fabricating a cylinder capacitor.
2. Description of Related Art
A dynamic random access memory (DRAM) is used to replace a conventional static random access memory (SRAM) to increase the integration of a memory circuit, and has been widely used in computer related industrials. Different from a memory cell in a SRAM, which stores data by its state of conductivity, a memory cell in a DRAM stores data by utilizing the state of charging of a capacitor.
As the development of microprocessors and software applications is advancing, a higher capacity of memory is also required to execute those advanced applications. However, for a conventional DRAM, as the integration of a DRAM circuit is increased, that is, the transistors are downsized, it becomes difficult to maintain an acceptable signal-to-noise ratio at storing charges into a capacitor. Even though reducing the capacitance of each capacitor in a DRAM cell is able to raise the signal-to-noise ratio, but the refreshing rate of each memory cell has to be increased accordingly.
Speaking of a signal memory cell of a DRAM, it contains at least a field effect transistor (FET) and a capacitor in order to store a bit of binary data. As referring to FIG. 1, a memory cell consists of a transistor 10 and a capacitor 11. To the transistor 10, the source of the transistor is connected to a corresponding bit line 12, the gate is connected to a corresponding word line 13, and the drain is connected to the storage electrode 14, or a so-called lower electrode, of a capacitor 11. The plate electrode 15, or a so-called upper electrode or a cell electrode, of the capacitor 11 is connected to a voltage source. Between the upper and lower electrodes, there is a dielectric layer 16 for storing charges.
Since the size of a capacitor is limited by the dimension of a memory cell, different structures, such as a trench capacitor, a cylinder capacitor, and a stack capacitor, are used to increase the capacitance of a capacitor without further occupying the substrate horizontally. Among the foregoing structures, the most commonly used are the cylinder capacitor and the stack capacitor that are designed to extend the storage electrode upward vertically for increasing the capacitance of the capacitor.
The fabrication process of a conventional cylinder capacitor is shown in the cross-sectional views of FIGS. 2A through 2G.
As shown in FIG. 2A, a oxide layer 21 and a silicon nitride layer 22 are formed on a substrate 20 in sequence, wherein the substrate 20 already contains a metal-oxide-semiconductor (MOS) transistor.
Referring to FIG. 2B, the silicon nitride layer 22 and the oxide layer 21 are patterned to form an opening 23 that exposes the substrate 20. Then, a conducting layer 24, polysilicon, is deposited on the silicon nitride layer 22 and filled in the opening 24. The polysilicon on the top of the silicon nitride layer 22 is removed by performing an etching back process, so that the top surface of the polysilicon layer 24 and the top of the silicon nitride layer 22 are coplanar, as shown in FIG. 2C.
Referring next to FIG. 2D, a oxide layer 25 is formed on the top of the silicon nitride layer 22 and the polysilicon layer 24, and patterned to form an opening 26, wherein the opening 26 exposes the polysilicon layer 24. Another conducting layer 27 is deposited conformal to the oxide layer 25 the opening 26, wherein the conducting layer 27 is electrically connected to the polysilicon layer 24 underneath. The entire foregoing structure is then covered by an oxide layer 28.
Referring to FIGS. 2E and 2F, a portion of the oxide layer 28 and the conducting layer 27 are removed by performing several etching processes to form a lower electrode of a capacitor that consists of the remaining conducting layer 27 and the polysilicon layer 24.
Referring next to FIG. 2G, a dielectric layer 29 and another conducting layer 30 are deposited on the substrate 20 in sequence to cover the structure on the substrate 20, wherein the conducting layer 30 is used as an upper electrode of a capacitor.
Since the size of a DRAM cell is decreased according to the increased integration of a DRAM, the amount of charges stored in a capacitor is also decreased. In the case that a capacitor of a DRAM cell cannot hold a certain amount of charges, the occurrence of soft errors due to the incident .alpha.-ray is increased as well. Therefore, it has been an objective to maintain the capacitance of a capacitor in a DRAM cell, in the mean time, also to downsize the device.
In the foregoing step of forming the opening 23, which includes patterning conventional photoresist on the oxide layer, tends toward causing defects such as blind contact due to the limitation of the exposure resolution.